MBR Partners is looking for a seasoned ASIC Design Engineer to spearhead the development of next-generation AI compute architectures in Dubai. This role is perfect for engineers who want their RTL code to drive real-world silicon powering large-scale AI workloads.
Role Overview: Building the Future of AI Silicon
If you thrive on optimizing micro-architecture for performance, power, and area, this position offers the chance to own end-to-end design cycles. You won’t just be writing Verilog; you’ll be collaborating with architects and firmware teams to ensure your designs survive the transition from simulation to production silicon.
The work involves everything from complex interconnects and compute clusters to critical PLLs. You will manage the full lifecycle—from initial architectural exploration and RTL implementation to timing closure and post-silicon validation.
Key Responsibilities
- Design Ownership: Lead the full-stack design of ASIC subsystems, including IP evaluation and integration.
- Performance Optimization: Make high-stakes trade-offs between area, power, and latency to improve AI economics at scale.
- Verification & Sign-off: Develop production-quality RTL (Verilog/SystemVerilog), run CDC/RDC analysis, and manage STA to ensure clean timing.
- Collaboration: Work alongside cross-functional teams, including compiler engineers, system validation experts, and security teams.
- Automation: Develop Tcl/Python scripts to streamline skew analysis and core-to-IO interfaces like PCIe, 400GE, and UCIe.
Qualifications You Need
This is an advanced role for engineers with a deep track record in silicon development. To be considered, you should bring:
- Experience: At least 7+ years of hands-on experience in RTL design and the ASIC development lifecycle.
- Core Skills: Expert-level proficiency in Verilog/SystemVerilog and familiarity with AMBA bus protocols (AXI, AHB, APB).
- Technical Breadth: Demonstrated success in complex IP integration, such as NoCs, GPUs, NPUs, or high-speed I/O.
- Timing Mastery: Strong skills in SDC authoring, STA, and formal equivalency checking.
- Bonus Points: Practical exposure to AI accelerator architectures (systolic arrays, dataflow) and HBM/GDDR integration is highly valued.
Why This Role Matters
In the competitive landscape of AI hardware, every microsecond counts. This role places you in a strategic position within the MBR Partners team to influence how modern AI workloads are processed. It is a rare opportunity to bridge the gap between abstract architectural concepts and high-performance, enterprise-grade silicon.
How to Apply
Ready to take the next step in your career? You can review the full details and initiate your application via the recruitment platform. Make sure your resume highlights your specific experience with high-speed interfaces and silicon bring-up.
Frequently Asked Questions (FAQ)
What is the primary location for this job?
This role is based in Dubai, United Arab Emirates, with the recruitment managed by MBR Partners.
What level of experience is required for this ASIC role?
You need at least 7 years of professional experience in RTL design and the full ASIC development lifecycle to be eligible for this position.
Does this role involve working with AI-specific hardware?
Yes, the position focuses on AI ASIC accelerator development, including work on compute clusters, systolic arrays, and high-bandwidth memory subsystems.